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19-2391; Rev 0; 4/02
+3.3V, 10.7Gbps Limiting Amplifier
General Description
The MAX3971A is a compact 10.7Gbps limiting amplifier. It accepts signals over a wide range of input voltage levels and provides constant-level output voltages with controlled edge speeds. It functions as a data quantizer with a 240mVP-P differential CML output signal with a 100 differential termination. The MAX3971A has a disable function that allows the outputs to be squelched if required by the application. The MAX3971A is designed to work with the MAX3970 transimpedance amplifier (TIA). The limiting amplifier operates on a single +3.3V supply and functions over a 0C to +85C temperature range. The MAX3971A is offered in die form and in a compact 4mm x 4mm 20-pin QFN package. o Single +3.3V Power Supply o 2mVP-P Input Sensitivity o 1.8ps Typical Deterministic Jitter (VIN = 800mVP-P) o Dice and 4mm x 4mm QFN Package Available o Output Disable Feature
Features
MAX3971A
Applications
VSR OC-192 Receivers 10Gbps Ethernet Optical Receivers 10Gbps Fibre Channel Receivers
PART MAX3971AUGP MAX3971AU/D
Ordering Information
TEMP RANGE 0C to +85C 0C to +85C PIN-PACKAGE 20 QFN-EP* Dice**
*EP = exposed pad **Dice are designed to operate over a 0C to +110C junction temperature (TJ) range, but are tested and guaranteed at TA = +25C. Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V 0.1F +3.3V CZGNDIN+ 0.1F IN+ 100 INGNDINOUT50 OUT+ 0.1F 50 CZ+ SUPPLY FILTER VCC1 VCC2 VCC3
TIA
0.1F
0.1F
MAX3970 MAX3971A
DISABLE
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+3.3V, 10.7Gbps Limiting Amplifier MAX3971A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC1, VCC2, VCC3 ......................-0.5V to +5.0 V Voltage at IN+, IN-, DISABLE, CZ+, CZ-, OUT+, OUT- .........................................+0.5V to (VCC + 0.5V) Differential Voltage Between CZ+ and CZ- ...........................1V Differential Voltage Between IN+ and IN-...........................2.5V Continuous Power Dissipation (TA = +85C) 20-Pin QFN (derate 20mW/C above +85C) .................1.3W Operating Ambient Temperature Range .............-40C to +85C Storage Temperature Range .............................-55C to +150C Die Attach Temperature...................................................+400C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, output load = 50 to VCC, TA = 0C to +85C, unless otherwise noted. All AC parameters are measured with a 223 - 1 PRBS pattern applied to the input at 10.7Gbps. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER Supply Current Small-Signal Bandwidth Input Sensitivity Input Overload Low-Frequency Cutoff SYMBOL ICC BW VIN-min VIN-max (Notes 1, 2) (Note 1) CZ = 0.1F (Note 1) 5mVP-P input (Notes 1, 3) Deterministic Jitter 10mVP-P input (Notes 1, 3) 800mVP-P input (Notes 1, 3) 1200mVP-P input (Notes 1, 3) Random Jitter Transition Time Data Input Impedance Data Output-Voltage Swing Data Output Voltage when Disabled Data Output Common-Mode Voltage Data Output Impedance Data Output Offset when DISABLE is High Disable Input Current DISABLE High Voltage DISABLE Low Voltage Disable Response Time VIH VIL 20 2 0.8 Single ended 42 tr, tf 20mVP-P < input < 1200mVP-P (Notes 1, 4) 20% to 80%, differential output (Note 1) Single ended Differential signal amplitude between OUT+ and OUTDifferential signal amplitude between OUT+ and OUT42 190 1200 60 5.2 3.5 1.8 1.9 0.6 20 50 240 0.25 VCC 75 50 75 30 58 200 60 75 16.0 14.0 7.0 11.0 1.1 30 58 400 50 psRMS ps mVP-P mVP-P mV mV A V V ns ps CONDITIONS MIN TYP 50 10 2 5 MAX 85 UNITS mA GHz mVP-P mVP-P kHz
Note 1: Guaranteed by design and characterization. Note 2: The output signal amplitude at the sensitivity is > .95 the amplitude with large input. Note 3: Deterministic jitter is measured with K28.5 pattern (0011 1110 1011 0000 0101) at 10.7Gbps. It is the peak-to-peak deviation from the ideal time crossing, measured at the zero-level crossing of the differential output. Note 4: For a bit-error rate of 10-12, the peak-to-peak random jitter is 14.1 the RMS random jitter.
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+3.3V, 10.7Gbps Limiting Amplifier
Typical Operating Characteristics
(VCC = +3.3V, output load = 50 to VCC, TA = +25C, unless otherwise noted.)
OUTPUT EYE DIAGRAM (INPUT SIGNAL = 10mVP-P, AT 10.7Gbps)
MAX3971A toc01
MAX3971A
OUTPUT EYE DIAGRAM (INPUT SIGNAL = 5mVP-P, AT 10.3Gbps)
MAX3971A toc02
OUTPUT EYE DIAGRAM (INPUT SIGNAL = 1200mVP-P, AT 10.3Gbps)
223 - 1PRBS
MAX3971A toc03 MAX39971A toc09 MAX3971A toc06
223 - 1PRBS
223 - 1PRBS
45mV/div
45mV/div
45mV/div
20ps/div
20ps/div
20ps/div
OUTPUT EYE DIAGRAM (INPUT SIGNAL = 800mVP-P, AT 10.7Gbps)
MAX3971A toc04
SUPPLY CURRENT vs. AMBIENT TEMPERATURE
58 56 SUPPLY CURRENT (mA) 54 GAIN (dB) 52 50 48 46 44 42 40
MAX3971A toc05
SMALL-SIGNAL GAIN
50 45 40 35 30 25 20 15 10 5 0 MAX3971A UGP
60
223 - 1PRBS
45mV/div
20ps/div
0
10
20
30
40
50
60
70
80
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FREQUENCY (GHz)
TEMPERATURE (C)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX3971A toc07
RANDOM JITTER vs. INPUT AMPLITUDE
MAX3971A toc08
DETERMINISTIC JITTER vs. INPUT AMPLITUDE
6 5 4 3 2 10.7Gbps, K28.5, VCC = +3V, TEMP = 85C
270 250 230 210 190 170 150 0 1 2 3 VIN (mVP-P) 4 5 6
3.5 3.0 RANDOM JITTER (psRMS) 2.5 2.0 1.5 1.0 0.5 0 1 10 100 1000
JITTER (psP-P)
VOUT (mVP-P)
1 0 10,000 1 10 100 1000 10,000 INPUT AMPLITUDE (mVP-P) INPUT AMPLITUDE (mVP-P)
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+3.3V, 10.7Gbps Limiting Amplifier MAX3971A
Typical Operating Characteristics (continued)
(VCC = +3.3V, output load = 50 to VCC, TA = +25C, unless otherwise noted.)
DETERMINISTIC JITTER vs. TEMPERATURE
10.7Gbps with K28.5 6 5 JITTER (psP-P) LOSS (dB) 4 3 2 1 0 0 10 20 30 40 50 60 70 80 AMBIENT TEMPERATURE (C) VIN = 800mV VIN = 5mV
MAX3971A toc10
INPUT RETURN LOSS (S11) (VCC = +3.3V)
MAX3971A toc11
OUTPUT RETURN LOSS (S22) (VCC = +3.3V)
-5 -10 -15 LOSS (dB) MAX3971A
MAX3971A toc12
7
0 -5 -10 -15 -20 -25 MAX3971A
0
-20 -25 -30 -35 -40
-30 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (GHz)
-45 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (GHz)
OUTPUT NOISE POWER (INPUT CONNECTED TO 50 TO GND)
MAX3971A toc13
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
MAX3971A toc14
INPUT COMMON-MODE REJECTION RATIO vs. FREQUENCY
VIN = VIN+ = VINMAX3971A toc15
-19.0 -19.1 NOISE POWER (dBm) -19.2 -19.3 -19.4 -19.5 -19.6 0 10 20 30 40 50 60 70 80 TEMPERATURE (C)
45
70 65 60 CMRR (dB) 55 50 45
40 PSRR (dB) 35
30
PSRR = -20log VOUT/VCC 10k 100k 1M FREQUENCY (Hz) 10M 100M
40
CMRR = -20log(VOUT/VIN) 100 1M 10M 100M 1G 10G
FREQUENCY (Hz)
4
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+3.3V, 10.7Gbps Limiting Amplifier
Pin Description
PIN 1 2 3 4 5, 7, 9, 10 6, 8, 11 12, 15 13 14 16 17 18 19 20 EP NAME GNDIN+ IN+ INGNDINN.C. GND VCC3 OUTOUT+ DISABLE VCC2 CZ+ CZVCC1 EXPOSED PAD Noninverting Input Signal Inverting Input Signal Input Ground for Shielding Input Signal IN-. Not connected internally. No Connection. Leave unconnected. Ground Output Circuitry Power Supply Inverting Output of Amplifier Noninverting Output of Amplifier When DISABLE is connected to VCC or left floating, outputs are disabled. When DISABLE is connected to GND, outputs are enabled. Power Supply to Circuitry other than Input and Output Circuits Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed Description section. Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed Description section. Input Circuitry Power Supply Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation. FUNCTION Input Ground for Shielding Input Signal IN+. Not connected internally.
MAX3971A
Detailed Description and Applications Information
Figure 1 is a functional diagram of the MAX3971A limiting amplifier. The signal path consists of an input buffer followed by a gain stage and output amplifier. A feedback loop provides offset correction by driving the average value of the differential output to zero.
CZ
Gain Stage and Offset Correction
The limiting amplifier provides approximately 42dB gain. The large gain makes the amplifier susceptible to small DC offsets, which cause deterministic jitter. A low-frequency loop is integrated into the limiting amplifier to reduce output offset, typically to less than 2mV. The external capacitor (CZ) is required for stability and to set the low-frequency cutoff for the offset correction loop. The time constant of the loop is set by the product of an equivalent 20k on-chip resistor and the value of the off-chip capacitor (CZ). For stable operation, the minimum value of CZ is 0.01F. To minimize patterndependent jitter, CZ should be as large as possible. For 10Gbps ethernet and SONET applications, the typical value of CZ is 0.1F. Keep CZ close to the package to reduce parasitic inductance.
CZ-
CZ+
DISABLE
MAX3971A
GNDIN+ IN+ 100 ININPUT AMPLIFIER
OFFSET CORRECTION AMP
LOWPASS FILTER
OUT+
CML Input Circuit
GAIN 42dB OUTPUT AMPLIFIER OUT-
GNDIN-
The input buffer is designed to accept CML input signals such as the output from the MAX3970 transimpedance amplifier. An equivalent circuit for the input is shown in Figure 2. For lowest deterministic jitter in all operating conditions, AC-coupling capacitors are recommended on the input.
Figure 1. Functional Diagram _______________________________________________________________________________________ 5
+3.3V, 10.7Gbps Limiting Amplifier MAX3971A
VCC1
+3.3V
GNDIN+
50
50
100k
IN+
INGNDIN-
ESD STRUCTURES
DISABLE
Figure 2. CML Input Equivalent Circuit
VCC3
20A
Figure 4. TTL Input Stage
50 50 OUT+ OUTDISABLE Q3 Q4 Q1 Q2 ESD STRUCTURES DATA
+3.3V
L
SUPPLY FILTER
0.001F
0.001F
0.001F
Figure 3. CML Output Equivalent Circuit
VCC1
VCC2
VCC3
CML Output Circuit
An equivalent circuit for the output network is shown in Figure 3. It consists of a pair of 50 resistors connected to VCC driven by the collectors of an output differential transistor pair (Q1 and Q2). The differential output signals are clamped by transistors Q3 and Q4 when the DISABLE input is high.
MAX3971A
Figure 5. Power-Supply Filter
DISABLE Function
A logic signal can be applied to the DISABLE pin to squelch the output signal. When the output is disabled, an offset is added to the output, preventing the following stage from oscillating, if DC-coupled. See Figure 4 for the input stage of the DISABLE function.
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_______________________________________________________________________________________
+3.3V, 10.7Gbps Limiting Amplifier
Layout Considerations
Circuit board layout and design can significantly affect the performance of the MAX3971A. Use good high-frequency techniques, including fixed-impedance transmission lines for the high-frequency data signal. Use a multilayer board with solid ground plane. Minimize the inductance between the MAX3971A and the ground plane. The MAX3971A uses three power-supply pins (VCC1, VCC2, and VCC3). The input circuitry of the MAX3971A is supplied by VCC1. The output drivers have a separate supply (VCC3), which usually has large pulsing currents. All other circuitry is powered by VCC2. It is possible to simply connect the three pins together. However, using a supply filter ensures better isolation of the input circuitry. For optimal isolation, Figure 5 shows a possible supplyfiltering circuit. Element L, a ferrite bead, provides isolation between a noisy VCC3 and a sensitive VCC1.
VCC1 CZ-
Pin Configuration
DISABLE VCC2 CZ+
MAX3971A
20 1 2 3 4 5
19
18
17
16 15 VCC3 14 OUT+
GNDIN+ IN+ INGNDINN.C.
MAX3971A
13 OUT12 VCC3 11 GND
6 GND
7 N.C.
8 GND
9 N.C.
10 N.C.
Chip Information
TRANSISTOR COUNT: 324 PROCESS: SiGe Bipolar SUBSTRATE: Electrically Isolated
20 QFN 4mm x 4mm
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+3.3V, 10.7Gbps Limiting Amplifier MAX3971A
Chip Topography
VCC1 CZCZ+ VCC2 DISABLE
VCC3 GNDIN+
OUT+ IN+
OUTIN0.052" (1.33mm) VCC3 GNDIN-
NC
GND
(0, 0) GND N.C. GND 0.042" (1.10mm) N.C. N.C.
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+3.3V, 10.7Gbps Limiting Amplifier
Chip Topography (continued)
MAX3971A PAD NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 X DIMENSION (m) 16 26 26 16 16 191 303 415 527 639 978 978 974 974 978 825 713 601 489 377 Y DIMENSION (m) 554 418 287 151 39 -92 -92 -92 -92 -92 67 179 315 446 582 647 647 647 647 647
MAX3971A
*
Pad dimensions: PASSIVATION OPENING: 94.4m 94.4m METAL: 102.4m 102.4m
*
All measurements specify the lower left corner of the pad. Refer to Application Note H Fan-08.0: Understanding Bonding Coordinates and Physical Die Size.
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+3.3V, 10.7Gbps Limiting Amplifier MAX3971A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12,16,20, 24L QFN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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